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125MHz WRITE PROGRAMMABLE TIMING EDGE VERNIER
FEATURES
s True 125MHz retrigger rate s Pin-compatible with Bt605 s 15ps delay resolution s Less than 1 LSB timing accuracy s Differential TRIGGER and delay WRITE inputs s Delay spans from 4 to 40ns s Compatible with 10KH ECL logic s Lower power dissipation 350mW typical s Available in 28-pin plastic (PLCC) or metal (MLCC) J-lead package
SY605 FINAL
DESCRIPTION
Micrel-Synergy's SY605 is an ECL-compatible timing vernier (delay generator) whose time delay is programmed via an 8bit code which is loaded via an independent "WRITE" input. The SY605 is fabricated in Micrel-Synergy's proprietary ASSETTM bipolar process. This device can be retriggered at speeds up to 125MHz, with a delay span as short as 4ns. At minimum span, the resolution is 4ns/255 = 15.7ps per step. The delay span is externally adjustable up to 40ns. The SY605 employs differential TRIGGER and WRITE inputs, and produces a differential OUTPUT pulse; all other control signals are singleended ECL. Edge delay is specified by an 8-bit input which is loaded into the device with the WRITE signal. The output pulse width will typically be 3.5ns. The SY605 is commonly used in Automatic Test Equipment to provide precise timing edge placement; it is also found in many instrumentation and communications applications. Micrel-Synergy's circuit design techniques coupled with ASSETTM technology result in not only ultra-fast performance, but allow device operation at lower power dissipation than competing technologies. Outstanding reliability is achieved in volume production.
BLOCK DIAGRAM
D0 - D7
8 8 LATCH DAC I/V
WRITE
+ - PULSE GEN
PIN CONFIGURATION
OUT OUT VCC VCC VCC NC
OUT
VBB
CE
D FF 0 = STOP 1 = RUN
LINEAR RAMP GENERATOR
25 24 23 22 21 20 19
D0 D1 D2 D3 D4 D5 D6
NC
26 27 28 1 2 3 4 5 6 7 8 9 10 11
18 17 16
COMP2 NC NC CE COMP1 WRITE VBB
TRIG
R
TOP VIEW PLCC J28-1
15 14 13 12
IEXT
WRITE
Rev.: E
D7
VEE1
TRIG VEE0
TRIG
IEXT
Amendment: /0
1
Issue Date: May, 1998
Micrel
SY605
PIN DESCRIPTION
D0 - D7 Data input pins (ECL compatible). On the falling edge of WRITE, D0 - D7 are latched into the DAC input register. D0 is the LSB. These inputs specify the amount of delay from the rising edge of TRIG to the output pulse. WRITE, WRITE Differential write inputs (ECL compatible). These inputs control the parallel data input latch. When WRITE is a logical one, the data latch is transparent. Data is latched on the falling edge of WRITE. A single-ended write may be used by connecting WRITE to VBB. CE Chip enable input (ECL compatible). CE must be a logical zero on the rising edge of TRIG to enable the device to respond to the trigger. If CE is floating, the trigger will always be enabled. TRIG, TRIG Differential trigger inputs (ECL compatible). The rising edge of TRIG is used to trigger the delay cycle if CE is a logical zero. If CE is a logical one, no operation occurs. It is recommended that triggering be performed with differential inputs. OUT, OUT Differential outputs (ECL compatible). IEXT Current reference pin. The amount of current sourced into this pin determines the span of output delay. The voltage at IEXT is typically -1.25V. COMP1, COMP2 Compensation pins. A 0.1F ceramic capacitor must be connected between COMP1 and VEE0, and COMP2 and VEE0 (see Figure 3). VEE Device power. All VEE pins must be connected. VCC Device ground. All VCC pins must be connected together. VBB A -1.36V (typical) output.
FUNCTIONAL DESCRIPTION
The output pulse generation cycle begins with the arrival of TRIG shown in Figure 1. The DAC values are latched by the rising edge of WRITE. Then, when TRIG transitions to a high and CE is low the linear ramp is initiated. When the ramp level reaches that of the DAC, the comparator initiates the pulse generator to produce an output pulse resets the ramp and the cycle is ready to begin again.
CE
TRIG
OUT
Figure 1.
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Micrel
SY605
ABSOLUTE MAXIMUM RATING(1)
Symbol VEE VI IOUT Parameter Power Supply (VCC = 0V) Input Voltage (VCC = 0V) Output Current -- Continuous -- Surge TA VEE Operating Temperature Range Operating Range
(2)
Value -8 to 0 0 to VEE 50 100 0 to +85 -5.7 to -4.2
Unit V V mA
C V
NOTES: 1. Beyond which device life may be impaired. 2. Parametric values specified at 10E Series: -4.75V to -5.5V
DC CHARACTERISTICS
TA = +0C Symbol VIH VIL VOH VOL IIH IIH IIL IIL DL IL VBB IEXT Parameter Input HIGH Voltage (10K) Input LOW Voltage (10K) Output HIGH Voltage (10K) Output LOW Voltage (10K) Input High Current (Vin = VIH max) TRIG, TRIG Input Low Current (Vin = VIL min) TRIG, TRIG Output Delay Spans Differential Linearity Error** Integral Linearity Error** VBB Output Voltage IEXT for Tspans Tspan = 4ns Tspan = 5ns Tspan = 10ns Tspan = 15ns Tspan = 20ns Tspan = 30ns Tspan with IEXT = 1.8 mA (Tspan = Tmax - Tmin) Tmin Minimum Delay Time* Data = 00, Tspan = 5ns Tspan = 10ns Tspan = 15ns Tspan = 20ns Tspan = 25ns Tspan = 30ns VEE Supply Current Min. -1170 -1950 -1020 -1950 -- -- -- -- -- -- -1.44 1.80 1.45 0.70 0.45 0.34 0.20 4.1 -- -- -- -- -- -- -- Typ. -- -- -975 -1755 100 100 100 100 0.84 1.16 -- 2.38 1.85 0.93 0.62 0.46 0.30 -- 2.8 3.4 4.0 4.6 5.2 5.8 -- Max. -840 -1480 -840 -1630 150 150 150 150 0.9 1.25 -1.25 2.80 2.40 1.20 0.80 0.60 0.40 6.5 3.8 4.9 6.0 7.1 8.2 9.3 100 MIn. -1130 -1950 -980 -1950 -- -- -- -- -- -- -1.44 1.80 1.45 0.70 0.45 0.34 0.20 4.1 -- -- -- -- -- -- -- TA = +25C Typ. -- -- -920 -1750 100 100 100 100 0.84 0.89 -1.35 2.38 1.85 0.93 0.62 0.46 0.30 -- 2.8 3.4 4.0 4.6 5.2 5.8 70 Max. -810 -1480 -810 -1630 150 150 150 150 0.9 1.0 -1.25 2.80 2.40 1.20 0.80 0.60 0.40 6.5 3.8 4.9 6.0 7.1 8.2 9.3 100 Min. -1070 -1950 -920 -1950 -- -- -- -- -- -- -1.44 1.80 1.45 0.70 0.45 0.34 0.20 4.1 -- -- -- -- -- -- -- TA = +70C Typ. -- -- -850 -1720 100 100 100 100 0.84 0.89 -- 2.38 1.85 0.93 0.62 0.46 0.30 -- 2.8 3.4 4.0 4.6 5.2 5.8 -- Max. -735 -1450 -735 -1600 150 150 150 150 0.9 1.0 -1.25 2.80 2.40 1.20 0.80 0.60 0.40 6.5 3.8 4.9 6.0 7.1 8.2 9.3 100 Unit mV mV mV mV A A A A LSB V mA mA mA mA mA mA ns ns ns ns ns ns ns mA
IEE
NOTE: 1. 10K series circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50 resistor to -2.0 volts.
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Micrel
SY605
AC CHARACTERISTICS
ECL input values are -0.9 to -1.7V, with input rise/fall times 2ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. OUT and OUT loading with 50 to -2.0V. Typical values are based on nominal temperature, i.e., and nominal voltage, i.e., - 5.2V.
TA = +0C Symbol fMAX tWI tWO tS Trigger Rate(1) Trigger Width High Output Pulse Width High Time Output Pulse Rise/Fall Time (20/80%) Output Pulse Spacing Span = 4ns @ 1 LSB Minimum Delay Time vs. Tspan Parameter Min. -- 2.0 2.5 -- 8.0 Typ. -- 1.0 3.5 550 -- 125 -- -- 2 2 60 -- -- -- -- -- Max. 125 -- 4.5 750 -- 220 40 157 -- -- -- -- -- -- -- -- -- 2.0 2.5 -- 8.0
TA = +25C Min. Typ. -- 1.0 3.5 550 -- 125 -- -- 2 2 60 -- -- -- -- -- Max. 125 -- 4.5 750 -- 220 40 157 -- -- -- -- -- -- -- -- Min. -- 2.0 2.5 -- 8.0
TA = +70C Typ. -- 1.0 3.5 550 -- 125 -- -- 2 2 60 -- -- -- -- -- Max. 125 -- 4.5 750 -- 220 40 157 -- -- -- -- -- -- -- -- Unit MHz ns ns ps ns ps/ns ns ns ps ps/C ps/C ps/V ns ns ns ns ns
T00 / ns (Tspan = 5 to 10ns)
--
4.0 15.7 -- -- -- 2.0 1.5 2.0 1.0 1.5
--
4.0 15.7 -- -- -- 2.0 1.5 2.0 1.0 1.5
--
4.0 15.7 -- -- -- 2.0 1.5 2.0 1.0 1.5
1 LSB 1 LSB
Output Delay Tspan (Tspan = Tmax - Tmin) Resolution (Tspan / 225) Tempo (5ns Span) Tspan /C Tmin /C Power Supply Rejection (Data = 0-FF HEX, Tspan = 5ns) CE Setup Time CE Hold Time WRITE Pulse Width High Time D0 - D7 Setup Time D0 - D7 Hold Time
tS tH tWH tDS tDH
NOTE: 1. See chart below:
Maximum Tspan and Trigger Rates Maximum Tspan (ns) Maintaining Linearity of 1 LSB 4.0 5.1 5.8 6.75 8.1 9.9 12.0 15.5 22.0 8.0 10.0 11.1 12.5 14.3 16.6 20.0 25.0 33.3 Minimum Trigger Periods (ns)
The information in this table is guaranteed but not 100% production tested. See Figure 2 for a graphical representation.
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Micrel
SY605
TIMING DIAGRAMS
tWI
TRIG tSU CE DELAY tWO tH
OUT
tS
tWH
WRITE
tDSU
tDH
D0 -D7
DATA
1 LSB Span vs. Trigger Rates
9 8 7
INL - 0.92LSB
Span (ns)
6 5 4 3 2 60 70 80 90
INL - 0.86LSB INL - 0.9LSB
INL - 1.14LSB
100 110 120 130
Frequency (MHz)
Figure 2.
5
Micrel
SY605
APPLICATION DIAGRAM
VEE1
VEE0
SY605
ZO = 50
-5.2V C3 C4 C2 C1
COMP1 WRITE COMP2 VCC I WRITE IEXT REXT VEXT
GROUND
-2.0V 50 ZO = 50
-2.0V 50 ZO = 50 ZO = 50
TRIG
-2.0V 50 ZO = 50
OUT
-2.0V 50 ZO = 50
TRIG
-2.0V 50
OUT*
-2.0V 50
REXT Calculation:
REXT = (VEXT + 1.25V)/IEXT For Example: If Tspan is around 15ns, then IEXT is around 0.6mA, (see DC Characteristic Table) and assume IEXT pin is tied to VCC with the resistor. REXT = 0 + 1.25V/0.6mA = 2.08K ohm
Location C1-C4 REXT Description 0.1F ceramic capacitor 1% metal film resistor (selected for proper Tspan) Vendor Part Number Erie RPE112Z5U104M50V CB301210 Dale CMF-55C
NOTE: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the SY605. All devices should be as close as possible to the SY605. Figure 3. Typical Connection Diagram and Parts List.
PRODUCT ORDERING CODE
Ordering Code SY605JC SY605JCTR Package Type J28-1 J28-1 Operating Range Commercial Commercial
6
Micrel
SY605
28 LEAD PLCC (J28-1)
Rev. 03
7
Micrel
SY605
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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